Efficient hardware implementations of low bit depth motion estimation algorithms

In this paper, we present efficient hardware implementation of multiplication free one-bit transform (MF1BT) based and constraint one-bit transform (C-1BT) based motion estimation (ME) algorithms, in order to provide low bit-depth representation based full search block ME hardware for real-time video encoding. We used a source pixel based linear array (SPBLA) hardware architecture for low bit depth ME for the first time in the literature. The proposed SPBLA based implementation results in a genuine data flow scheme which significantly reduces the number of data reads from the current block memory, which in turn reduces the power consumption by at least 50% compared to conventional 1BT based ME hardware architecture presented in the literature. Because of the binary nature of low bit-depth ME algorithms, their hardware architectures are more efficient than existing 8 bits/pixel representation based ME architectures

Are RNGs Achilles’ heel of RFID Security and Privacy Protocols ?

Security and privacy concerns have been growing with the increased usage of the RFID technology in our daily lives. To mitigate these issues, numerous privacy-friendly authentication protocols have been published in the last decade. Random number generators (RNGs) are commonly used in RFID tags to provide security and privacy of RFID protocols. RNGs might be weak spot of a protocol scheme and misusing of RNGs causes security and privacy problems. However, having a secure RNG with large entropy might be a trade-off between security and cost for low-cost RFID tags. Furthermore, a RNG used in RFID tag may not work properly in time. Therefore, we claim that vulnerability of using a RNG may deeply influence the security and privacy level of the system. To the best of our knowledge, this concern has not been considered in RFID literature. Motivated by this need, in this study, we first revisit Vaudenay\u27s privacy model which combines the early models and presents a new mature and elegant privacy model with different adversary classes. Then, we enhance the model by introducing a new oracle, which allows analyzing the usage of RNGs in RFID protocols. We also analyze a couple of proposed protocols under our improved model

Shot-cut detection for B&W archive films using best-fitting kernel

A novel shot-cut detection method for black and white (B&W) archive films, employing the best-fitting kernel between two consecutive image frames is proposed in this paper. The best-fitting kernel, obtained using least squares, is used to estimate the second frame of each successive frame pair. The absolute frame difference between estimated and original image frames is utilized as criterion to decide a candidate scene-cut. A double thresholding approach, consisting of global and local adaptive thresholds, is used in this stage. Obtained candidates are forwarded to a confirmation stage to exclude single-frame defects, frequently encountered in archive film sequences. Experimental results show that the proposed method gives favorable result for B&W degraded archive films, compared to methods proposed in the literature

An all binary sub-pixel motion estimation approach and its hardware architecture

Motion estimation (ME) is the most computationally intensive part of a video coding system. Therefore it is very important to reduce its computational complexity. In this paper, a novel all-binary approach for reducing the computational complexity of sub-pixel accurate ME is proposed. An efficient hardware architecture for the proposed all-binary sub-pixel accurate motion estimation approach is also presented. The proposed hardware architecture has significantly low hardware complexity and therefore very low power consumption. It can process 720p video frames at 30 fps in a pipelined fashion together with the integer ME hardware. Therefore, it can be used in real-time low power video coding systems required by many mobile consumer electronics devices

MVBLA based design of constrained 1-bit transform based motion estimation algorithm

In this work a novel hardware proposed for Constrained 1-bit Transform based motion estimation to facilitate real time operation. The designed system occupies a small area in a general purpose FPGA fabric and it is therefore efficient to implement a whole video coding architecture on a single FPGA chip. The designed system can perform ME operation for a 2048×1152 pixel sized image frame at a speed of 20 frames/second